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ADVANCE INFORMATION
Integrated Circuit Systems, Inc.
ICS843101-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
FEATURES
* One 312.5MHz nominal LVPECL output * Selectable crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal or LVCMOS single-ended input * Output frequency can be varied in 2% steps from nominal * VCO range: 560MHz - 690MHz * RMS phase jitter @ 312.5MHz, using a 25MHz crystal (1.875MHz-20MHz): <1ps (typical) design target * Output supply modes Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V * 0C to 70C ambient operating temperature * Available in both standard and lead-free RoHS-complaint packages
GENERAL DESCRIPTION
The ICS843101-312 is a low phase-noise frequency margining synthesizer with freHiPerClockSTM quency margining capability and is a member of the HiPerClockSTM family of high performance clock solutions from ICS. In the default mode, the device nominally generates a 312.5MHz LVPECL output clock signal from a 25MHz crystal input. There is also a frequency margining mode available where the device can be programmed, using the serial interface, to vary the output frequency up or down from nominal in 2% steps. The ICS843101-312 is provided in a 16-pin TSSOP.
IC S
BLOCK DIAGRAM
OE CLK
Pullup Pulldown
PIN ASSIGNMENT
VEE S_LOAD S_DATA Q S_CLOCK SEL nQ OE VCCA VCC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 MODE VCCO Q nQ VEE CLK XTAL_OUT XTAL_IN
1
25MHz
/P OSC
0
XTAL_IN XTAL_OUT SEL
Phase Detector
VCO
560 - 690MHz
/N
Pulldown
/M
ICS843101-312
16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View
S_CLOCK S_DATA S_LOAD MODE
Pulldown Pulldown Pulldown Pulldown
Serial Control
The Advance Information presented herein represents a product currently in design or being considered for design. The noted characteristics are design targets. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843101AG-312
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OCTOBER 18, 2005
ADVANCE INFORMATION
Integrated Circuit Systems, Inc.
ICS843101-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
quency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by an output divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle. The relationship between the crystal input frequency, the M divider, the VCO frequency and the output frequency is provided in Table 1. When changing back from frequency margining mode to nominal mode, the device will return to the default nominal configuration that will provide 312.5 MHz output frequency. Serial operation occurs when S_LOAD is HIGH. Serial data can be loaded in either the default mode or the frequency margining mode. The 6-bit shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. After shifting in the 6-bit M divider value, S_LOAD is transitioned from HIGH to LOW which latches the contents of the shift-register into the M divider control register. When S_LOAD is LOW, any transitions of S_CLOCK or S_DATA are ignored.
VCO (MHz) 562.5 575 587.5 600 612.5 625 637.5 650 662.5 675 687.5 Output Divider (N) 2 2 2 2 2 2 2 2 2 2 2 Output Frequency (MHz) 281.25 287.5 293.75 300 306.25 312.5 318.75 325 331.25 337.5 343.75 % Change -10.0 -8.0 -6.0 -4.0 -2.0 0 2.0 4.0 6.0 8.0 10.0
FUNCTIONAL DESCRIPTION
The ICS843101-312 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A 25MHz fundamental crystal is used as the input to the on chip oscillator. The output of the oscillator is fed into the pre-divider. In frequency margining mode, the 25MHz crystal frequency is divided by 2 and a 12.5MHz reference frequency is applied to the phase detector. The VCO of the PLL operates over a range of 560MHz to 690MHz. The output of the M divider is also applied to the phase detector. The default mode for the ICS843101-312 is 312.5MHz output frequency using a 25MHz crystal. The output frequency can be changed by placing the device into the margining mode using the mode pin and using the serial interface to program the M feedback divider. Frequency margining mode operation occurs when the MODE input is HIGH. The phase detector and the M divider force the VCO output frequency to be M times the reference fre-
TABLE 1. FREQUENCY MARGIN FUNCTION TABLE
XTAL (MHz) 25 25 25 25 25 25 25 25 25 25 25 Pre-Divider (P) 2 2 2 2 2 2 2 2 2 2 2 Reference Frequency (MHz) 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 Feedback Divider (M) 45 46 47 48 49 50 51 52 53 54 55
M-Data (Binary) 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111
SERIAL LOADING
S_CLOCK S_DATA
t
M5 M4
S
M3
M2
M1
M0
t
S
t
H
S_LOAD
Time
FIGURE 1. SERIAL LOAD OPERATIONS
843101AG-312
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OCTOBER 18, 2005
ADVANCE INFORMATION
Integrated Circuit Systems, Inc.
ICS843101-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
Type Description Negative supply pins. Pulldown Controls the operation of the Serial input. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. Pulldown LVCMOS/LVTTL interface levels. Clock in serial data present at S_DATA input into the shift register on the Pulldown rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Select pin. When HIGH, selects CLK input. Pulldown When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. Output enable pin. Controls enabling and disabling of Q/nQ outputs. Pullup LVCMOS/LVTTL interface levels Analog supply pin. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Pulldown LVCMOS/LVTTL clock input. Differential output pair. LVPECL interface levels.
TABLE 2. PIN DESCRIPTIONS
Number 1, 12 2 3 4 5 6 7 8 9, 10 11 13, 14 15 Name VEE S_LOAD S_DATA S_CLOCK SEL OE VCCA VCC XTAL_IN, XTAL_OUT CL K nQ, Q VCCO Input Input Input Input Input Power Power Input Input Ouput Power Power
Output supply pin. MODE pin. LOW = default mode. HIGH = frequency margining mode. 16 MODE Input Pulldown LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
843101AG-312
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OCTOBER 18, 2005
ADVANCE INFORMATION
Integrated Circuit Systems, Inc.
ICS843101-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 4A. OE CONTROL INPUT FUNCTION TABLE
Input OE 0 1 Outputs Q , nQ HiZ Enabled
TABLE 4B. SEL CONTROL INPUT FUNCTION TABLE
Input SEL 0 1 Selected Source XTAL_IN, XTAL_OUT CLK
TABLE 4C. MODE CONTROL INPUT FUNCTION TABLE
Input Mode 0 1 Condition Q, nQ Default Mode Frequency Margining Mode
TABLE 4D. SERIAL MODE FUNCTION TABLE
Inputs S_LOAD L H S_CLOCK X S_DATA X Data Serial inputs are ignored. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are latched. Conditions
L X NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
843101AG-312
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OCTOBER 18, 2005
ADVANCE INFORMATION
Integrated Circuit Systems, Inc.
ICS843101-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 89C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO IEE ICC ICCA ICCO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Core Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 TBD TBD TBD TBD Maximum 3.465 3.465 3.465 Units V V V mA mA mA mA
TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%,VCCO = 2.5V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO IEE ICC ICCA ICCO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Core Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 2.375 Typical 3.3 3.3 2.5 TBD TBD TBD TBD Maximum 3.465 3.465 2.625 Units V V V mA mA mA mA
TABLE 5C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO IEE ICC ICCA ICCO
843101AG-312
Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Core Supply Current Analog Supply Current Output Supply Current
Test Conditions
Minimum 2.375 2.375 2.375
Typical 2.5 2.5 2.5 TBD TBD TBD TBD
Maximum 2.625 2.625 2.625
Units V V V mA mA mA mA
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OCTOBER 18, 2005
ADVANCE INFORMATION
Integrated Circuit Systems, Inc.
ICS843101-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
Test Conditions VCC = 3.3V VCC = 2.5V VCC = 3.3V VCC = 2.5V Minimum Typical 2 1. 7 -0.3 -0.3 Maximum VCC + 0.3 VCC + 0.3 0.8 1.7 150 5 -5 -150 20 Units V V V V A A A A ns/v
TABLE 5D. LVCMOS / LVTTL DC CHARACTERISTICS, TA = 0C TO 70C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage CLK, SEL, S_DATA, S_LOAD, S_CLOCK, MODE OE CLK, SEL, S_DATA, S_LOAD, S_CLOCK, MODE OE t/v Input Transistion Rise/Fall Rate OE, SEL, S_CLOCK, S_DATA, S_LOAD, MODE
IIH
Input High Current
VCC = VIN = 3.465 or 2.625V VCC = VIN = 3.465 or 2.625V VCC = 3.465V or 2.625V, VIN = 0V VCC = 3.465V or 2.625V, VIN = 0V
IIL
Input Low Current
TABLE 5E. LVPECL DC CHARACTERISTICS, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1. 0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal. Test Conditions Minimum Typical Maximum 25 50 7 100 Units MHz pF W Fundamental
TABLE 7. INPUT FREQUENCY CHARACTERISTICS, TA = 0C TO 70C
Symbol Parameter CLK fIN Input Frequency XTAL_IN/XTAL_OUT S_CLOCK Test Conditions Minimum Typical 25 25 50 Maximum Units MHz MHz MHz
843101AG-312
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OCTOBER 18, 2005
ADVANCE INFORMATION
Integrated Circuit Systems, Inc.
ICS843101-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
Test Conditions Mode = LOW 312.5MHz, (1.875MHz - 20MHz) 20% to 80% Minimum Typical 312.5 TBD TBD 50 10 10 10 Maximum Units MHz ps ps % ns ns ns
TABLE 8A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol fOUT t jit(O) tR / t F odc Parameter Output Frequency RMS Phase Jitter ; NOTE 1 Output Rise/Fall Time
Output Duty Cycle S_DATA to S_CLOCK tS Setup Time S_CLOCK to S_LOAD S_DATA to Hold Time tH S_CLOCK NOTE 1: Characterized using a 25MHz cr ystal.
TABLE 8B. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%,VCCO = 2.5V5%, TA = 0C TO 70C
Symbol fOUT t jit(O) tR / t F odc Parameter Output Frequency RMS Phase Jitter ; NOTE 1 Output Rise/Fall Time Mode = LOW 312.5MHz, (1.875MHz - 20MHz) 20% to 80% Test Conditions Minimum Typical 312.5 TBD TBD 50 10 10 10 Maximum Units MHz ps ps % ns ns ns
Output Duty Cycle S_DATA to S_CLOCK tS Setup Time S_CLOCK to S_LOAD S_DATA to Hold Time tH S_CLOCK NOTE 1: Characterized using a 25MHz cr ystal.
TABLE 8C. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%,VCCO = 2.5V5%, TA = 0C TO 70C
Symbol fOUT t jit(O) tR / t F odc Parameter Output Frequency RMS Phase Jitter ; NOTE 1 Output Rise/Fall Time Mode = LOW 312.5MHz, (1.875MHz - 20MHz) 20% to 80% Test Conditions Minimum Typical 312.5 TBD TBD 50 10 10 10 Maximum Units MHz ps ps % ns ns ns
Output Duty Cycle S_DATA to S_CLOCK tS Setup Time S_CLOCK to S_LOAD S_DATA to Hold Time tH S_CLOCK NOTE 1: Characterized using a 25MHz cr ystal.
843101AG-312
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OCTOBER 18, 2005
ADVANCE INFORMATION
Integrated Circuit Systems, Inc.
ICS843101-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
2.8V0.04V 2V
VCC, VCCA, VCCO
Qx
SCOPE
VCC, VCCA VCCO
Qx
SCOPE
LVPECL
nQx
LVPECL
VEE
nQx
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2V
Phase Noise Plot
Noise Power
VCC, VCCA, VCCO
Qx
SCOPE
LVPECL
nQx
Phase Noise Mask
VEE
f1 Offset Frequency f2
-0.5V 0.125V
RMS Jitter = Area Under the Masked Phase Noise Plot
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ 80% Clock Outputs 80% VSW I N G 20% tR tF
odc = t PW t PERIOD x 100%
Q
t PW
t
PERIOD
20%
OUTPUT RISE/FALL TIME
843101AG-312
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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OCTOBER 18, 2005
ADVANCE INFORMATION
Integrated Circuit Systems, Inc.
ICS843101-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843101-312 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA. The 10 resistor can also be replaced by a ferrite bead.
3.3V or 2.5V VCC .01F VCCA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843101-312 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 3 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 27p X1 18pF Parallel Crystal XTAL_IN C2 27p
Figure 3. CRYSTAL INPUt INTERFACE
843101AG-312
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ADVANCE INFORMATION
Integrated Circuit Systems, Inc.
ICS843101-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50 FOUT FIN
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
Zo = 50 84 84
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
843101AG-312
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ADVANCE INFORMATION
Integrated Circuit Systems, Inc.
ICS843101-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
843101AG-312
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OCTOBER 18, 2005
ADVANCE INFORMATION
Integrated Circuit Systems, Inc.
ICS843101-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER RELIABILITY INFORMATION
TABLE 9.
JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
137.1C/W 89.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843101-312 is: TBD
843101AG-312
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OCTOBER 18, 2005
ADVANCE INFORMATION
Integrated Circuit Systems, Inc.
ICS843101-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 10. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153 www.icst.com/products/hiperclocks.html
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843101AG-312
OCTOBER 18, 2005
ADVANCE INFORMATION
Integrated Circuit Systems, Inc.
ICS843101-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 11. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature ICS843101AG-312 3101A100 16 Lead TSSOP tube -40C to 85C ICS843101AG-312T 3101A100 16 Lead TSSOP 2500 tape & reel -40C to 85C ICS843101AG-312LF TBD 16 Lead "Lead-Free" TSSOP tube -40C to 85C ICS843101AG-312LFT TBD 16 Lead "Lead-Free" TSSOP 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS complaint.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843101AG-312
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